Integrated circuits have substantially increased in complexities over the years. The technology is moving towards smaller and smaller device structures. The extension of the technology to obtain narrow line widths in the range of one micrometer or less by extending conventional photolithography techniques such as electron beam, ultraviolet light, or X-ray lithography is becoming more difficult and expensive.
Other narrow device structure techniques have been developed to overcome this problem. One such technique is described in H. B. Pogge in IBM Technical Disclosure Bulletin, November 1976, Vol. 19, No. 6, pgs. 2057-2058 entitled "Narrow Line Widths Masking Methods". This method involves the use of a porous silicon followed by the oxidation of the porous silicon. Another technique is described by S. A. Abbas et al., in the IBM Technical Disclosure Bulletin, September 1977, Vol. 20, No. 4, pgs. 1376-1378. This method describes the use of polycrystalline silicon masking layers which are made to mask by first using intermediate mask of oxidation blocking material, such as silicon nitride in the formation of the polycrystalline silicon. Line dimensions below about 2 micrometers may be obtained by this technique.
Methods for forming narrow dimensioned, for example, sub-micrometer regions on the silicon body are disclosed by U.S. Pat. Nos. 4,209,349 and 4,209,350 by I. T. Ho et al., and U.S. Pat. No. 4,234,362 by J. Riseman. These patents involve the formation of substantially horizontal surfaces and substantially vertical surfaces on the silicon body and then forming a vertical layer of a very narrow dimension on the substantially vertical surfaces. This layer may be formed by initially depositing a very narrow dimensioned layer on both the substantially horizontal and substantially vertical surfaces followed by an anisotropic reactive ion etching process to remove the horizontal layer while leaving the vertical layer substantially intact. The vertical layer dimension is adjusted depending upon the original thickness of the layer applied. Alternatively, the vertical layer may be formed by the oxidation of a side edge of a polysilicon layer which has its top surface masked by a oxidation resistant coating such as silicon nitride as described in the S. G. Barbee et al., IBM Technical Disclosure Bulletin, Aug. 19, 1982, Vol. 25, No. 3B, pgs. 1448-1449 or as shown in the H. B. Pogge, U.S. Pat. No. 4,256,514. In these ways a narrow dimension region as one micrometer or less may be obtained.
A further major related problem in the very dense integrated circuit technology is how to electrically contact the various elements and devices of such narrow dimensions in the integrated circuit. It is known to use highly doped polycrystalline silicon as a source of a dopant for regions of monocrystalline silicon to form PN junctions therein. The polycrystalline silicon can either be removed or allowed to become part of the device as the electrical contact for the region formed by the out-diffusion from the polycrystalline silicon. Such processes are taught, for example by H. J. Evans et al, U.S. Pat. No. 3,978,515; J. H. Scott, Jr., U.S. Pat. No. 3,460,007; D. M. Duncan, U.S. Pat. No. 3,664,896; S. Tauchi et al., U.S. Pat. No. 3,484,313 and the aforementioned I. T. Ho et al., U.S. Pat. No. 4,209,350. However, these patents are either silent on the method for the next level metallurgy to the electrical contact or have a second level metallurgy directly above the polycrystalline silicon electrical contact to the PN junction.
Other workers in the field have addressed the electrical contact in other ways, such as U.S. Pat. No. 3,600,651 by providing lateral polycrystalline silicon contacts to a monocrystalline silicon active region. The polycrystalline silicon is then contacted at a more convenient location laterally away from the active region. N. G. Anantha et al., U.S. Pat. No. 4,236,294 also uses the technique of a polycrystalline silicon contact to a PN junction and then a contact to the polycrystalline layer at some convenient distance laterally away from that PN junction. The H. S. Bhatia et al., U.S. Pat. No. 4,507,171 filed Aug. 6, 1982 entitled "Method For Contacting A Narrow Width PN Junction Region" describes further methods for making contact to a narrow width PN junction region by electrically contacting a horizontal conductive layer at a convenient location. The horizontal conductive layer in turn contacts a vertical conductive layer which makes contact to the element of the integrated circuit.
There has been significant effort in the integrated circuit field to develop processes for making sub-micrometer channel length field effect transistor with a high degree of channel length control. Examples of this work are described in "A New Edge-defined Approach for Sub-micrometer MOSFET Fabrication" by W. R. Hunter et al., IEEE Electron Device Letters, Vol. EDL-2 No. 1, January 1981, pp. 4.noteq.6; "Sub-micrometer Polysilicon Gate CMOS/SOS Technology" by A. C. Ipri et al., published in IEEE Transactions on Electron Devices, Vol. ED-27, No. 7, July 1980, pp. 1275-1279; and "A Novel Sub-micron Fabrication Technique" by T. N. Jackson et al., published in IEDM 1979 Conference Volume, pp. 58-61. The first paper relies on the reactive ion etching technique to form a sidewall silicon dioxide. The second paper utilizes a technique involving lateral diffusion of boron. The third method uses the plating of a metal on the edge of a conventionally patterned metal layer. Other short channel field effect transistor devices are illustrated in the U.S. Pat. No. 4,419,809 to J. Riseman et al., U.S. Pat. No. 4,430,791 to R. C. Dockerty and U.S. Pat. No. 4,445,267 to F. H. De La Moneda et al.
A particularly effective MOSFET configuration allowing densities and performance higher than that heretofore available in such devices is described in "A New Short Channel MOS FET with Lightly Doped Drain" by Saito et al., in Denshi Tsushin Rengo Taikai (Japanese) April 1978, pp. 2-20. The LDD N channel MOSFET includes, in addition to the channel separating implanted N+ source and drain regions, sub-micrometer diffused N- regions, which increases the channel breakdown voltage or snapback voltage and reduces device drain junction electron impact ionization (and thus, hot electron emission) by spreading the high electric field at the drain pinchoff region into the N- region. This allows either an increase in power supply voltage or reduction in channel length at a given voltage to achieve performance enhancement. An improved process for making such a device is given in U.S. Pat. No. 4,366,613 by S. Ogura and P. J. Tsang in which the N- LDD region of the device is formed by a controlled N- ion implantation and the forming of sub-micrometer wide SiO.sub.2 sidewall spacers abutting to the gate. Other lightly doped drain processes are given in the before mentioned I. T. Ho and J. Riseman U.S. Pat. No. 4,209,349; U.S. Pat. No. 4,209,350 and U.S. Pat. No. 4,419,810 to J. Riseman. These patents also show self-aligned diffused regions formed by outdiffusion from layers formed on the surface of a semiconductor substrate into the substrate. In the above mentioned Ogura and Tsang's patent, the polycrystalline silicon gate plate of the LDDFET is formed by conventional lithographic process. Its minimum achievable length is limited by the capability of the lithographic tool used. Further, there is no highly dense way to electrically contact the elements of the field effect devices. In the present invention the minimum achievable device gate length is no longer limited by the lithographic tools but can be set by design requirement. Devices with channel length less than one micrometer can be readily made with conventional photolithographic tools.
It is therefore desirable to provide a high density, short channel field effect transistor which can be fabricated with submicron channel length and which can be effectively electrically contacted.